> The HLS generated verilog is name mangled

Chisel, SpinalHDL, Clash, Migen, Amaranth aren't HLS

Most of the time, if you get some verilog out of those tools with mangled names, it can be because of bad coding practice.

Here is some examples about how to preserve good names for SpinalHDL : https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/S...

> FWIW, that's not true, you can write it as one:

While technicaly you are right, i think you missed the spirit of what the doc was saying.

You may write it all in a single process, but you will always have duplicated code blocks, especialy if those 3 types of hardware (ff,ff with reset, comb) share assignements with the same condition.

On this talk : - https://youtu.be/f-b4QOzMyfU?t=300 - https://youtu.be/f-b4QOzMyfU?t=492 => yes and no

The industry lack's of wide profiles (hardware engineer with good software understanding) is really hurting any new innovative HDL

Yeah, just saw that by chance last night. Darn shame.

For what it's worth, I don't thin Chisel is really standardizable as it stands, but something like it could be.

Checkout SpinalHDL it keep much more of your hardware description semantic inside the generated Verilog

Wrong, it was implemented from scratch. Look the same, but was implemented in a very different philosophy. SpinalHDL is from my opinion much better.

I was exactly in the same mood some years ago, until i triey one of those HDL alternative.

Honnestly, i haven't realy think about it. Not a constraining one, but more something like :

Do what ever you want with it, but if you find a bug, please tell me, and if you use it in a project which has a lot of money, please, share a bit with opensource guys, don't be too greedy ^^

Cached an uncached memory access are currently staticaly specified by range :

https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/s...

From 0xF000000 to 0xFFFFFFFF access will be uncached.

Yes a standard would be great, with all the feature provide by those embedded HDL, but i'm realy not sure the industry could make it. #systemverilog

Yes kind of, SpinalHDL is a from scratch fork