Hard to believe the claims here, when no real empirical data is presented. Has the process been integrated in any foundry (even test fab)? Have they been able to tape out even an old chip, like 180nm, one with copper, one with graphene? If so, at wafer size and what yield? How many metal layers can be processed (global or local interconnects - if it's pressure based, how will the bottom most layers be affected as the interconnect stack is built up?

Also, back side power delivery + new materials like Ru will keep interconnect roadmap going for a while.

Articles like this read nothing more than fluff pieces.