wafer.space has just opened our first pooled manufacturing run of GF180MCU with the purchase deadline of 28th Nov 2025.
Think of it like OHS Park for silicon!
You provide a 20mm2 design in the open source GF180MCU technology and you get back 1,000 parts. You can used an existing template or build something completely yourself with either open source or proprietary tooling (no required pad ring or management CPU).
I’ve noticed there are a bunch of tiny chip houses in China, like 5-10 employees, that have their own chip portfolios and even transistors. Typically in niche markets, of course. I’d love to see that kind of foundational innovation in the USA.
The designs are still more in the MCU size, but you have to start somewhere!
The Google open MPW program also had 10 runs with 40 projects published at http://foss-eda-tools.googlesource.com/third_party/shuttle/ -- All the submissions had to be open source and there were 1000+ of those. I did try pitching to multiple Google Research groups that continuing the open MPW funding would grow the available designs which have been manufactured and that was useful for AI training but didn't get any bites.
The now defunct Efabless also ran a number of challenges in this space which got pretty good results, see https://efabless.com/challenges
Our company www.precisioninno.com is growing proving professional support for OpenROAD much like companies providing support around Linux do. My presentation at the birds of a feather highlights the engagement levels.
I stumbled upon the Tomu (and hence submitted this story) specifically because I wanted to get my hands on a small/cheap FPGA via the Fomu. Probably picking up the Somu as a Yubikey replacement too. Keep up the awesome work!
I have a Google Doc at <https://j.mp/softcpus-on-fpgas> which includes a bunch of information about what type of performance has been achieved on modern Xilinx FPGAs.
When did you last check? The Yosys+VPR toolchain currently supports a full Linux capable SoC with Ethernet and DDR memory on the Arty A35T (which has a Xilinx Artix 7 part), see the example at https://f4pga-examples.readthedocs.io/en/latest/building-exa...
A few months ago. Looks like DSP (hardware multiply-accumulate units) is partially supported now if VexRiscv is synthesizing, but there's still some open issues on their tracker about whether they understand them fully or not.
I afraid I don't recall the status of DSP blocks in the open source toolchains for Xilinx hardware. Even if the basics are supported I'm sure there are plenty of DSP features that are not.
Many configurations of VexRISCV work fine without using the DSP blocks (and has been working for 2+ years), so not sure that is relevant.
While the news seems to focuses on ML and RISC-V, there is a huge amount of *other* activity in the silicon space. With [Google working to improve the open source EDA tools + PDKs while also providing free manufacturing](https://opensource.googleblog.com/2022/05/Build%20Open%20Sil...) there are lots of opportunities.
The "new" FPGA companies like GowinSemi and RapidSilicon are also creating some pretty cool parts.
Think of it like OHS Park for silicon!
You provide a 20mm2 design in the open source GF180MCU technology and you get back 1,000 parts. You can used an existing template or build something completely yourself with either open source or proprietary tooling (no required pad ring or management CPU).