AFAIK, an FPGA board is not enough, you also need the "compiled netlist" from the Verilog files, clock configuration and routing info, tailored to the specific FPGA/board you choose.
Kinda, sorta? This is like saying "a computer is not enough, you need a binary." What's here is the source code in Verilog. Once this is compiled by a Verilog toolchain, this produces a netlist (set of gates) which is synthesized into an actual bitstream (proprietary gate configuration file) for a specific FPGA hosted on a specific board.
In this case, the project isn't very documented but it looks like fairly generic Verilog without a lot of vendor specific extensions. So, what you need is a Verilog toolchain which can synthesize the source code into a netlist, and then into a bitstream, and the right set of extra code to target an actual physical piece of hardware.
But, the overall setup looks pretty simple and generic, so it should (hopefully) be possible to synthesize to your board of choice by reimplementing run.v and memstubs.v towards an actual hardware configuration.
Basically what you'd want to do to start trying to run this on real hardware is to build a hosting environment which wired the inputs and outputs from `md_board.v` into the real hardware provided in your environment, possibly by integrating other soft-IP (ie - you could attach a cartridge emulator of some sort to the cartridge lines, your choice of video encoder to the video output, and so on).
Aka the software that comes with the FPGA vendor. I think Intel, AMD, the Chinese vendors and some parts from Microchip have the software available for free.
Parallel, and much worse. Everyone out in the software land with their open languages, free compilers, and package repositories doesn't know how bad it is in FPGA land.
